This invention relates to electronic computer systems and the like, and more particularly relates to improved methods and apparatus for achieving a video display having high resolution.
Related U.S. patent applications are: application Ser. No. 633,385 entitled "Video System Controller with a Row Address Override Circuit" by Jeffrey C. Bond and Robert C. Thaden, application Ser. No. 633,386 entitled "Video Memory Controller" by Robert C. Thaden, Jeffrey C. Bond, James C. Moravec, Karl M. Guttag, Raymond Pinkham and Mark Novak, application Ser. No. 633,367 entitled "State Machine Standard Cell" by Robert C. Thaden and Mark W. Watts, application Ser. No. 633,389 entitled "X Y Addressing" by Karl M. Guttag, Jerry Van Aken, Jeffrey C. Bond, Rudy Albachten and Mark Novak, application Ser. No. 633,383 entitled "Video System with Single Memory Space for Instructions, Program Data and Display Data" by Karl M. Guttag, Raymond Pinkham and Mark Novak, application Ser. No. 633,388 entitled "Single Chip Video System with Separate Clocks for Memory Controller and CRT Controller" by Robert C. Thaden and Jeffrey C. Bond and application Ser. No. 633,387 entitled "Video Memory Controller Support Storage of Data From an External Source" by Jeffrey C. Bond and Robert C. Thaden.
It is conventional to present the output from a computer as an image on the screen of a cathode ray tube or the like. The screen is actually composed of a collection of dots or "pixels", and the image is therefore produced by selecting and illuminating those pixels necessary to form the desired image. If the image sought to be presented is merely a simplistic pattern of numbers or other symbols, this may be achieved with a relatively limited number of pixels. However, if a more complex image (with a greater resolution) is desired, then a screen must be chosen which has a substantially greater number of pixels.
It should be understood that each pixel used to form the image is illuminated by a separate output data signal from the processing section of the computer, and that an increase in resolution requires a screen having a greater number of pixels. More particularly, since each video data signal must also be stored before being transferred to the video screen, an increase in image resolution also requires that the data storage section have a corresponding increase in the number of memory cells for receiving and holding all of these data signals.
If a different screen having an increased number of pixels is employed for the purpose of enhancing the resolution of the image displayed on the screen, this will not by itself cause a disproportionate increase in the overall cost of the system. However, the size or capacity of the memory component or circuit is a significant factor in the cost of the system, and an increase in the resolution of the image being presented effectively decreases the time interval available to effect a complete transfer of all of the data signals between the storage and the video section.
There have been many attempts and proposals for overcoming or mitigating these disadvantages. In particular, a larger storage unit may be selected to accommodate the increased number of input signals, but as hereinbefore explained, such a unit is inherently expensive, and its use in home computer systems will disproportionately increase the costs of such computer systems. The technology is available to provide specially designed memory units capable of fast access for higher data velocity, but such units are even more expensive than slower access memory units.
Alternatively, an increase in data storage capacity may be achieved by simply adding additional memory units. However, this not only increases the overall cost of the system, since each memory unit is a separate storage component this tends to increase the length of the time required to transfer video data to the pixels.
It has been proposed to mitigate part of the problem which arises when the data storage is composed of a plurality of separate random-access memory units or "chips", by interconnecting them in parallel with a shift register, whereby all of the units may be unloaded and their contents transferred to the shift register at the same time. The data in the shift register is then sequentially clocked to the pixels at the proper video data rate. Although this technique has been extremely beneficial in reducing the data transfer cycle to that corresponding to a single memory chip, it does not attack the problem of increased cost. Moreover, since the storage circuit is composed of memory units of standard design, there will inherently be more cells in the storage unit than there are pixels on the video screen, and whenever the storage is unloaded into the video section, it is necessary to unload more cells than are actually required to produce the image.
The control circuits for the prior art systems required three different controllers, one for handling system memory, one for handling of text information and one for handling of graphic information. These systems often resulted in bottlenecks at the video memory.
The next subsystem is only required if the performance of the bit-mapped controller subsystem is insufficient to handle text in a reasonable period of time. Today in a number of products, the text and graphics are combined into one subsystem. These systems, however, have the drawback that they must have physically separate data buses between the least part of the system memory and the display memory. In one example--part of the main system memory is in a shared memory space with the display data, there is a separate isolated data bus that connects to a high speed ROM that is used to contain important (for performance) routines.
Due to the fact that most display devices must be constantly refreshed with display data, there is a need for a relatively constant "background" task that continually transfers the contents of the display memory to the display device. This "background" with normal RAMs can monopolize the data bus into and out of the RAMs for as much as 85% (percent). With the multiport video RAM type device (such as Texas Instrument Inc's TMS4161 for example), the amount of data bus requirement needed for the display refresh task can be dropped down to less than 3%. On the other hand, the aforementioned bottleneck created when other types of RAMs are used.
In systems using conventional memories for holding the display data it is imperative that the significant portion of the processor's main system memory not be on the same physical data bus as the display data bus, or else the system performance would be substantially reduced. For example if the processor were connected on a bus where 80% of the bus cycles were allocated to display refresh, the overall system performance could be degraded by as much as 5 times (due to only getting 20% or 1/5th of the accesses).
The solutions to date, using conventional memories for the display data, have been to isolate at least a significant portion (if not all) the CPU's main system memory data bus from the display memory data bus. This isolation lets the processor run significantly faster on the isolated system memory bus that it can out of the display memory bus. In some cases, such as systems using a NEC7220 manufactured by Nippon Electric Corporation, the isolation of the display memory is such that the processor has only very limited access to the display memories.